1. Field of Invention
The present invention relates to a circuit structure for dual resolution in a display apparatus.
2. Description of Related Art
LCD is one kind of popular flat panel display devices. There are two resolution modes in LCD, normal resolution mode and half resolution mode. In general, LCD is displayed under the normal resolution mode. In some cases, for example, for power-saving or low resolution requirement, LCD will be displayed under the half resolution mode.
FIGS. 1a and 1b show the definition of unit pixel in the normal resolution mode and the half resolution mode, respectively. Referring to FIG. 1a, in the normal resolution mode, one unit pixel includes one individual pixel, with R, G and B three sub-pixels. Referring to FIG. 1b, in the half resolution mode, one unit pixel includes four individual pixels. In FIGS. 1a and 1b, symbols “R”, “G” and “B” refer to R/G/B sub-pixels and “R1”, “R2”, and “R3” refer to first, second and third pixel rows. As known, one individual pixel includes three sub-pixels, or said R/G/B sub-pixels. By defining different unit pixel in FIGS. 1a and 1b, dual resolution function is made.
Two kinds of vertical scan signals are used to define different unit pixel under different resolution modes. FIG. 2a and FIG. 2b show two kinds of vertical scan signals, respectively. In FIG. 2a, to define the unit pixel under the normal resolution, the vertical scan signal scan one pixel row in one pulse. In FIG. 2b, to define the unit pixel under the half resolution, the vertical scan signal scan two pixel rows in one scan pulse.
Taking an LCD panel with 640 pixel rows * 480 channels for example. In this LCD panel, 640 vertical scan signals are required to scan pixel rows. In normal resolution mode, a resolution of 640*480 is displayed. In half resolution mode, a resolution of 320*240 is displayed.
A cost effective and well performance circuit configuration for dual resolution modes in the LCD apparatus is needed.